3D MOSFET Case Study Summary

1. Why the effective channel width is more at the source end as compared to the drain end in a biased FET?
When a positive voltage is applied to the gate relative to the substrate (which is connected to the source in the case), positive charges are in effect deposited on the gate metal. In response, negative charges are induced in the underlying Si, by the formation of a depletion region and a thin surface region containing mobile electrons. These induced electrons form channel of the FET, and allow current to flow from drain to source.
Since electrons are electrostatically induced in the p-type channel region, the channel becomes less p-type, and therefore the valence band moves down, farther away from the Fermi level. Reduces the barrier

With a neat sketch, discuss the working principle of 3D MOSFET. What are its advantages as compared to conventional MOSFET? 3D transistor uses a single gate stacked on top of two vertical gates which allows electrons to travel three times of the surface area without increasing the size of the gate . The Gate is terminal that turns the transistor on and off , and store charges which make the channel conductive by acting as a capacitor.it creates an inversion layer between the source and the drain where electrons can flow this happen when the gate is charged.
On the three sides of a vertical fin structure 3D or tri-gate transistors forms a conducting channels which provides fully depleted operation and tighter control on the channel.
When the transistor is in on state the additional control enables as much transistor current flowing as possible, and when it is in the off state(to minimize power) is close to zero as possible , and enables the transistor to switch very quickly between the two states due to improved sub-threshold slope and increased inversion layer area provides higher drive currents.
Advantages :
1- Dramatic performance gain at low operating voltage ,better than Bulk Planar transistor 37% performance increase at low voltage >50% power reduction at constant performance