Activity 3.1 Interconnection Structures Essay

Activity 3.1 - Interconnection structures - The Bus [1 hour]

Activity Details

In this activity, you are to open at least two computers of different computer architecture models complete the following:-

Name the computer architecture widely used by modern computers

From the the computer architecture model you are using identify the following:

Number of data buses

Number of address buses

Number of control buses

Identify the type of connection for each I/O device and list the type of connection, e.g ISA, PCI, USB, COM port, etc.

Indicate what kind of data each of the I/O devices may send through the data bus.

Conclusion

There are different buses, input/output devices, ports, USB, COM ports and that these are different for different computer

It represents the process by which the computer is expected to retrieve (fetch) an instruction from its memory, decodes it to determine what action the instruction requires before carrying out the actions. This instruction cycle is done sequentially, that is, one instruction is processed completely before another one is fetched (started).

The different instruction sets may make different CPU’s to have different cycles. They are, however, similar in the following ways:- ( "Instruction Cycle." Instruction Cycle. Web. 15 Mar. 2016. Available at http://www.digplanet.com/wiki/Instruction_cycle )

The next instruction to be processed will be fetched from the memory address and this address is the one that is stored in the program counter (PC). This address is then stored in the instruction register (IR). When this happens the program counter will then point to the next instruction that will be read at the next cycle.

The next activity will be to decode the instruction found in the instruction register (IR) in order to understand what action is required. This is done by the