Incredible Logic Essay

Abstract—Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in

Power dissipation is one of the most important criteria in VLSI design, optimizing the amount of power dissipated is the main requirement in low power VLSI design. Reversible logic has the ability to reduce the amount of power being dissipated and finds extensive use in numerous other technologies such as quantum computing [1], nanotechnology, optical information processing [2], low power CMOS design [3], DNA computing and bioinformatics. Reversible gates have a unique input-output mapping because of which bit loss can be recovered whereas in conventional logic, information is lost once the input is applied and cannot be recovered from its corresponding output. Whenever there is information loss KTln2 joules of energy is dissipated for every bit. This was asserted by R Landauer in 1960 [4], here T is absolute temperature and K is Boltzmann’s constant. Since there is no information loss in reversible logic, the amount of power dissipated is considerably less when compared to conventional logic. Hence, there is a high possibility of reducing power dissipation to minimal levels by implementing digital circuits using reversible logic gates. Synthesis of reversible circuits is different from conventional ones. Few conditions [1] have to be satisfied for the synthesis of reversible circuits. The conditions are as