# Arithmetic Logic Lab Report

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CHAPTER 1 INTRODUCTION In the design of digital processer and application specific system Digital arithmetic operations are very important. Floating Point Arithmetic and logic Unit in Digital System FPGA implementation has been the most widely researched area in recent years separately and together. Separately many new architectures of ALU implementation have been proposed. As far as floating point unit or DSP block is concerned, it has been one of the most complex units for implementation on FPGA. But with the help of VHDL these implementations have become very easy now a day. The computation has become very easy for very…show more content…
The implemented arithmetic unit has a 32-bit processing unit which allows various arithmetic operations such as Addition, Subtraction, Multiplication and division on floating point numbers. Implemented arithmetic unit is a part of a computer system, specially designed to carry out operations on floating point numbers. Numbers during square measure painted is multiple of base of binary numbers. The illustrated range of the digit is increased by its base with exponent power. For representing floating numbers the IEEE 754 standard is employed in digital system. Arithmetic logic unit may be a digital circuit that performs arithmetic and logical operations and executes the commands consequently. The Arithmetic logic unit may be an elementary building block of the central processing unit of a pc and also the inputs to the ALU measure the information to be operated on and a code from the control unit indicating that operation to…show more content…
in the bit 46 in the intermediate product). Since the inputs are normalized numbers then the intermediate product has the leading one at bit 46 or 47. If the leading one is at bit 46 (i.e. to the left of the decimal point) then the intermediate product is already a normalized number and no shift is needed. If the leading one is at bit 47 then the intermediate product is shifted to the right and the exponent is incremented by 1. Normalization is quoth to be a sinequanon block for the entire design. When 48 bit output product is obtained from the vedic multiplier block, then the entire 2p bit result has to be normalized first in order to get correct answer. The output should be in 1. Form .The decimal point is suppose to be place after first Two MSB bits. Accordingly the output has to be metamorphose into the above alluded form. When decimal point shifts towards left hand side of result accordingly add 1 to the output of denormalizer & if the decimal point shifts towards right hand side of result