Digital Design Flow Case Study

4.3 Secure Digital Design Flow
The design goal in the development of SABL standard cells is to assure that all internal nodes of the pull-down circuit are associated to one of the external output ports when differential voltage is applied to the input ports. The design mechanism is a transformation step that converts the location of the transistors in the DPDN. As a result, the number of total devices remains the same. This may result in the increase in the depth of entire evaluation. The process of designing a specific SABL DPDN representing a logical function f is composed of following 5 steps:
1. Make identification of the two logic expressions A and B that constitutes the logical function f. The outcome would be an AND operation, A•B,

f = A•B f = A + B or case II f = A + B f = A • B
One expression is representing the AND type function, the other is representing OR type function. In the DPDN, the AND type function is executed as a series composition and the OR type as a parallel composition. At this abstraction level, the internal nodes are present only in the series composition.
In case I, we perform transformation of the parallel connection into A • B + B, put network B at the bottom of the A•B connection and share network B between the two branches A.B and A • B + B,
In case II, we perform transformation of the parallel connection into A • B + B , put network B at the bottom of the A • B connection and share network B between the two branches
A . B and A . B + B.
This has resulted in the DPDN which has the connection of the internal node of the series implementation to the output node.
4. Repeat the same process for the logical expressions A and B until the network reduces to only 1 transistor.
5. Substitute the

To satisfy the condition that in each cycle, the same amount of charge is consumed, the charging current must be kept constant. This will happen only in the case when at each internal node both the true input signal and the complement input signal takes control of separate single transistor that charges that particular node. Whether it is the true signal or its complement that controls the transistor, the total charging time for the internal nodes is the time required to precharge the output ports of the preceding gate. This requirement has been fulfilled by the special DPDN. We have performed the simulation by applying random input sequence for the duration of 500 clock cycles at a clock frequency of 100MHz and measured the total power dissipation that has been consumed in each operation cycle. From the generated 500 samples, the Normalized Power Deviation (NPD) and the Normalized Standard Deviation (NSD) have been calculated. NSD, whose value lies in the ranges from 0 to 1. NPD is defined as the difference between the maximum power dissipation and the minimum power dissipation normalized with respect to the maximum power dissipation. NSD is defined as the standard deviation normalized with the mean or average value of the power dissipation. The closer NPD and NSD are to 0, the more amount of power trace measurements are required and the measuring devices have to be