Reversible Logic Research Paper

Abstract- Power dissipation is one of the main issues in VLSI circuits. In recent years, Reversible logic gives a better solution for reducing power dissipation in system. Reversible logic has one-to-one mapping between input and output vectors. It has been used in various emerging applications like low power CMOS, Quantum computers etc. In the proposed work, the sequential circuits such as flip flop and shift registers are designed which enhanced performance by reducing area and power in terms of gate count, garbage outputs, and constant inputs. Detection of faults such as stuck-at-1 and stuck-at-0 fault which are occurred simultaneously by using minimum test vectors is also proposed in this paper.
Keywords—Reversible logic, Flip flops, Stuck-at-faults,

Reversible logic overcomes this drawback. The process of running the system in the backward direction is called reversible logic. 00 00 01 01 10 11 11 10 Fig 1: Reversible mapping For a gate to be reversible, the logic function it realizes has to be bijective. That is, there must be a one-to-one mapping between inputs and outputs as shown in fig 1. There are two rules in reversible logic:
• In reversible circuit fan out is not allowed, that is, each output will be used only once.
• For each input pattern there should be a unique output pattern. Lastly the circuit should be acyclic. Some of the reversible gates are Fredkin gate, Toffoli gate, sayem gate etc. Conservative logic is a property in which there is a equal number of 1s in the input and output as shown in table 1. It is called as reversible conservative logic when there is a equal number of 1s in the input and the output and have one-to-one mapping between input and output [1].

Table 1.Conservative logic
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1

A P=A

B Q=A’BAC C R=A’BACD D S=ABA’CD

Fig 5.Sayem Gate

A B C D P Q R
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 0 1 0
0 1 0 1 0 1 1
0 1 1 0 0 0 1
0 1 1 1 0 0 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1