Five Stage MIPS Architecture

ABSTRACT
In this project we have implemented a 5 stage MIPS architecture. MIPS is a RISC microprocessor architecture. The MIPS Architecture define 16-bit general purpose registers (GPRs). The CPU uses byte addressing for word accesses from the instruction memory and must be aligned on a byte boundary divisible by four (0, 4, 8 …). MIPS is a load/store architecture, meaning that all operations are performed on operands held in the processor registers and the main memory can only be accessed through the load and store instructions (e.g. LDR, STR). A load instruction loads a value from memory into a register. A store instruction stores a value from a register to memory. The load and store instructions use the value in the register/immediate field

First the PC value is used as an address to index the instruction memory which supplies a 32-bit value of the next instruction to be executed. This instruction is then divided into the different fields shown in instruction format table. The instructions opcode field bits [31-26] are sent to a control unit to determine the type of instruction to execute. The type of instruction then determines which control signals are to be asserted and what function the ALU is to perform, thus decoding the instruction. The instruction register address fields Rt bits [25 - 21], Rs bits [20 - 16], and Rd bits [15-11] are used to address the register file. The register file supports two independent register reads and one register write in one clock cycle. The register file reads in the requested addresses and outputs the data values contained in these registers. These data values can then be operated on by the ALU whose operation is determined by the control unit to either compute a memory address (e.g. load or store), compute an arithmetic result (e.g. add, and or sub), or perform a compare (e.g. branch). If the instruction decoded is arithmetic, the ALU result must be written to a register. If the instruction decoded is a load or a store, the ALU result is then used to address the data memory. The final step writes the ALU result or memory value back to the register file.

Pipelining, a standard feature in RISC processors, is a technique used to improve both clock speed and overall performance. Pipelining allows a processor to work on different steps of the instruction at the same time, thus more instruction can be executed in a shorter period of time. If the datapath is divided into different modules, and combined without pipeline registers then each module must wait for the previous one to finish before it can execute, thereby completing one instruction in one long clock cycle. When the MIPS processor is pipelined, during a single clock cycle each one of those modules or stages is in