1051 Words5 Pages

V. EXPERIMENTAL SETUP & RESULTS
The proposed dual T-NPC, dual PMSM topology and its modulation and control strategy are evaluated on an experimental setup as shown in Fig. 13. The experimental setup consists of two three-level T-NPC inverters feeding a dual three-phase 16 pole PMSM. The following capabilities of the proposed topology have been validated: 1) balancing DC-link voltages, 2) reduced output current distortion and 3) reducing capacitor RMS current. The motor input currents have been regulated by controlling the output voltages of the inverters. The control strategies are implemented using OPAL-RT based real time prototyping tool. Operational time-step is kept constant at 25 µs. The parameters of the experiments are as follows: dc-link*…show more content…*

- The proposed topology and control strategy reduces the positive DC-bus current ripple. This will reduce the ripple experienced by a battery source, feeding the inverter. As the topology and the control scheme achieves balanced DC-link voltages without using conventional capacitor balancing algorithms, the topology avoids additional switching instances associated with the conventional algorithms. This provides the topology an additional degree of freedom to use various switching loss reduction schemes. VII. CONCLUSION This paper proposes a dual three-level T-NPC inverter fed dual PMSM topology for low-voltage, high-power applications. Both simulation and experimental results show a significant improvement over the conventional single T-NPC inverter fed PMSM drive. The proposed topology and its interleaved PWM control strategy are capable of maintaining balanced DC-link capacitor voltages both during steady-state and transient conditions. Moreover, due to the control strategy, the current stress of the DC-link capacitors is also reduced by

- The proposed topology and control strategy reduces the positive DC-bus current ripple. This will reduce the ripple experienced by a battery source, feeding the inverter. As the topology and the control scheme achieves balanced DC-link voltages without using conventional capacitor balancing algorithms, the topology avoids additional switching instances associated with the conventional algorithms. This provides the topology an additional degree of freedom to use various switching loss reduction schemes. VII. CONCLUSION This paper proposes a dual three-level T-NPC inverter fed dual PMSM topology for low-voltage, high-power applications. Both simulation and experimental results show a significant improvement over the conventional single T-NPC inverter fed PMSM drive. The proposed topology and its interleaved PWM control strategy are capable of maintaining balanced DC-link capacitor voltages both during steady-state and transient conditions. Moreover, due to the control strategy, the current stress of the DC-link capacitors is also reduced by

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