Nt1310 Unit 6 Lab 1

From the design specifications, we know that Q = 0 if DG = 01 and Q = 1 if DG = 11 because D must be equal to Q when G = 1. We assign these conditions to states a and b. When G goes to 0, the output depends on the last value of D. Thus, if the transition of DG is from 01 to 10, the Q must remain 0 because D is 0 at the time of the transition from 1 to 0 in G. If the transition of DG is from 11 to 10 to 00, then Q must remain 1. First, we fill in one square belonging to the stable state in that row. Next a dash is entered in the squares, where both inputs change simultaneously. Finally remaining squares associated unstable states are filled in. Step 2. Primitive flow table is reduced to a smaller number of rows if two or more stable states are placed in the same row of the flow table (merging a number of stable states in the same row). This is done in the following table.

The states b, e, and f can also be merged into one row. Finally c and d can be replaced by a, e and f can be replaced by b. New reduced table and final reduced table are shown below.
Step 3. In order to obtain the circuit described by the reduced flow table, it is necessary to assign to each state a distinct binary value. This assignment converts the flow table into a transition table. Binary state assignment must be made to ensure that the circuit will be free of critical races. Assigning 0 to state a and 1 to state b in the reduced flow table, we obtain the transition table given below, which is, in fact, a map for the excitation variable Q+. The logic diagram of the gated latch is also shown below.
Assigning Output to Unstable