Vedic Mathematics Research Paper

High performance Neuro-computers using Vedic Mathematics Yamuna SV, Anshika, Nidhi Goel, S.Indu
Electronics and Communication Department
Delhi Technological University
Delhi, INDIA

Abstract-Artificial Neural Network has been considered to speed up processing due to its parallel architecture and the numerous mathematical computations involved for processing any input. Neuromorphic chips are supposed to be much faster than current computers at processing sensory data and learning from it. By far, the most often-stated reason for the development of custom neurocomputers is that conventional (i.e. sequential) general-purpose processors do not fully exploit the parallelism inherent in neural-network models and that highly parallel architectures

They can also be trained to solve that are difficult for conventional computers or human beings. The artificial neural networks consist of massively parallel network and require parallel architecture for high speed operations in real time applications.
The use of Vedic mathematics lies in the fact that it reduces the typical calculations in conventional mathematics into very simple one. This is so because the Vedic formulae are claimed to be based on the natural principles on which the human mind works. Vedic mathematics is a methodology of arithmetic rules that allow more efficient speed implementation. The technologies like ANN & Vedic mathematics (multiplier) are the two main technologies which can increase the processing speed.
In this paper, features of ANN & Vedic multiplier are used to estimate the performance of ANN with Vedic multiplier against normal multiplier. Also, the hardware implications of both the schemes are being done. Initially, a brief introduction about ANN and Vedic multiplier with Urdhva Triyakbhyam is given. The next section explains about the design and hardware implementation with simulation results of the work. The last section deals with the comparison of the proposed implementation with the standard neural

Block Diagram of 4x4 bit Vedic Multiplier

V. PROPOSED HARDWARE ARCHITECTURE OF A SINGLE NEURON USING VEDIC MULTIPLIER

Fig.6. Proposed Architecture

The proposed hardware is almost similar to a standard non-linear neuron except for the multiplier. Here the standard multiplier is replaced with a Vedic multiplier which multiplies the inputs with weights. Fig 6 shows the proposed architecture of a single neuron which has been designed using Vedic multiplier instead of standard multiplier to achieve higher speed in designing neurocomputers.
VI. RESULTS
A. Simulation Results
For the purpose of evaluation, performance of a single neuron with standard multiplier and Vedic multiplier were compared. The hardware implementation is carried out using VHDL. For implementation, testing and simulation purpose, Xilinx ISE 6.1 with ModelSim simulation tools were used. Spartan II family has been chosen as target device. The simulation and synthesis results are as follows.