Pentium 4 Block Diagram Analysis

MICROARCHITECTURE OF PENTIUM 4 Figure 1: Basic microarchitecture block diagram Pentium 4
A fast processor requires balancing and tuning of many computer architecture features that complete a microprocessor to perform at its peak. Figure 1 shows the basic Intel NetBurst microarchitecture of the Pentium 4 processor. As shown in the diagram, there are four main sections: the in-order front end, the out-of-order execution engine, the integer and floating-point execution units, and the memory subsystem. In Order Front End
The in-order front end is the part of the processor to fetch the upcoming instructions to be executed in the program and prepares them to be used later in the machine pipeline. It plays a role to supply a high-bandwidth stream

The top-left portion of the diagram shows the front end of the machine. The middle of the diagram illustrates the out-of-order buffering logic, and the bottom of the diagram shows the integer and floating-point execution units and the L1 data cache. On the right of the diagram is the memory subsystem.
The front end of the Pentium 4 processor consists of several units as shown in the upper part of Figure 4. It has the Instruction TLB (ITLB), the front-end branch predictor (labeled here Front-End BTB), the IA-32 Instruction Decoder, the Trace Cache, and the Microcode ROM.
Trace Cache (a.k.a. L1 cache)
Trace Cache The Trace Cache is the primary or Level 1 (L1) instruction cache of the Pentium 4 processor and delivers up to three uops per clock to the out-of-order execution logic. Most instructions in a program are fetched and executed from the Trace Cache. Only when there is a Trace Cache miss does the NetBurst microarchitecture fetch and decode instructions from the Level 2 (L2) cache. This occurs about as often as previous processors miss their L1 instruction cache. The Trace Cache has a capacity to hold up to 12K uops. It has a similar hit rate to an 8K to 16K byte conventional instruction